Built-in self-test tri-state architecture

Details Built-in self-test tri-state architecture Built-in self-test tri-state architecture

1991-10-28

1996-04-30

Ramirez, Ellis B.

Excavating

364489, 364490, G01R 102

Patent

active

055131905

ABSTRACT:
A circuit architecture for driving a tri-state bus in a logic circuit that uses a built-in self-test (BIST) mechanism. The architecture includes tri-state drivers which have circuitry to inhibit other drivers from driving the bus when another driver is driving the bus. The architecture includes circuitry to pullup the bus or to allow the bus to retain the last state it was driven to when none of the drivers is driving the bus. This circuitry also drives the bus to a known state during testing of the logic circuit.

REFERENCES:
patent: 4176258 (1979-11-01), Jackson
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4680761 (1987-07-01), Burkness
patent: 4691161 (1987-09-01), Kant et al.
patent: 5109382 (1992-04-01), Fukunaka
patent: 5159263 (1992-10-01), Yaguchi
Stroud, "Automated BIST for Sequential Logic Synthesis" IEEE Design & Test of Computers, Dec. 1988, pp. 22-32.

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