Built-in self-test technique for read-only memories

Details Built-in self-test technique for read-only memories Built-in self-test technique for read-only memories

1990-02-06

1992-02-25

Smith, Jerry

Excavating

G11C 2900

Patent

active

050919083

ABSTRACT:
Self-testing of a read only memory (10') containing an m.times.n+1 array of single-bit storage cells (12') is accomplished by first loading the bits of a preselected quotient string into the n+0 column of the memory. The quotient string is typically preselected to yield an all-zero residue if no errors are present. Thereafter, a first polynomial division is performed on the entire contents of the memory by sequentially shifting out of the bits in the cells in each successive ROM row in a right-to-left direction into a separate one of the n+1 inputs of a bidirectional multiple input shift register (18'). A second polynomial division is then performed on the m.times.n contents of the memory (10') by sequentially shifting the bits out of each successive row into the shift register (18') in a left-to-right direction. As each row of bits is shifted into the shift register (18') during the second polynomial division, the register generates a quotient bit which is exclusively OR'd with a corresponding one of the quotient bits stored in the n+1.sup.th column of the memory, allowing for errors in the memory to be detected. At the conclusion of the second polynomial division, there remains in the register a residue, also indicative of the errors in the memory.

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