Built-in-self-test scheme for testing multiple memory elements

Details Built-in-self-test scheme for testing multiple memory elements Built-in-self-test scheme for testing multiple memory elements

1994-04-11

1995-12-12

Beausoliel, Jr., Robert W.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365201, G11C 2900

Patent

active

054758157

ABSTRACT:
An apparatus for efficiently testing a plurality of memory devices at the board level. The logic for the present invention is minimal and can be placed on a controller chip within the board design. In addition, the interconnect lines between the controller chip and each of the plurality of memory devices can also be tested. Finally, the present invention requires minimal setup time and performs a functional test of the memories in a very short period of time.

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