Built in self test input generator for programmable logic arrays

Details Built in self test input generator for programmable logic arrays Built in self test input generator for programmable logic arrays

1985-05-13

1987-06-09

Fleming, Michael R.

Excavating

371 21, 371 25, G06F 1100

Patent

active

046726101

ABSTRACT:
A built in self test input generator (BISTIG) for programmable logic arrays (PLAs) providing exhaustive fault coverage, but requiring additional space of only 8 to 15% of the PLA area. The BISTIG contains a test vector generator and a product term control, each of which has a sequence generator and associated decoder. The sequence generators generate log.sub.2 (N) and log.sub.2 (M) test vectors for the test vector generator and the product term control respectively, where N is the number of inputs to the PLA and M is the number of product terms connecting the first level of the PLA with the second level of the PLA.

REFERENCES:
patent: 4380811 (1983-04-01), Gotze
patent: 4517672 (1985-05-01), Pfeiderer et al.
patent: 4525714 (1985-06-01), Still et al.
patent: 4571724 (1986-02-01), Belmondo
S. Bozorgui-Nesbat, et al. "Lower Overhead Design for Testability of Programmable Logic Arrays," IEEE 1984 International Design Test Conference, (publication of papers) pp. 856-865.
H. Fujiwara, et al. "A Low Overhead, High Coverage, Built-in, Self-Test PLA Design," VLSI Design Laboratory, Dept. of Electrical Engineering, McGill University, Report No. 84.13, 1984.
R. Truer, et al. "An Implementation of a New, Built-in, Self-Test PLA Design," VLSI Design Laboratory, Dept. of Electrical Engineering, McGill University, Report No. 84.14, 1984.

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