Built-in self-test hierarchy for an integrated circuit

Details Built-in self-test hierarchy for an integrated circuit Built-in self-test hierarchy for an integrated circuit

2006-02-28

2006-02-28

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C714S733000

Reexamination Certificate

active

07005873

ABSTRACT:
A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.

REFERENCES:
patent: 5381419 (1995-01-01), Zorian
patent: 5570374 (1996-10-01), Yau et al.
patent: 5978947 (1999-11-01), Kim et al.
patent: 6237123 (2001-05-01), Kim et al.

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