Excavating
Patent
1994-06-29
1997-06-10
Beausoliel, Jr., Robert W.
Excavating
371 224, 371 24, 371 251, G06F 1100
Patent
active
056383827
ABSTRACT:
A processor with a built in self test function that provides intermediate self test results is disclosed including at least one logic array and a test circuit for each logic array coupled to generate a logic array signature during a built in self test of the processor. The processor further comprises a set of internal registers including a performance register that stores the logic array signature and a register that stores a pass/fail indication for the built in self test of the processor. The internal registers also store a pass/fail indication for a cache memory built in self test and a pass/fail indication for a constant read only memory built in self test.
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DesRosier Peter J.
Krick Robert F.
Beausoliel, Jr. Robert W.
Intel Corporation
Iqbal Nadeem
LandOfFree
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