Built-in self test for system in package

Details Built-in self test for system in package Built-in self test for system in package

2008-07-01

2008-07-01

Nguyen, Ha (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07394272

ABSTRACT:
A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.

REFERENCES:
patent: 5517515 (1996-05-01), Spall et al.
patent: 6111414 (2000-08-01), Chatterjee et al.
patent: 6465336 (2002-10-01), Gabara et al.
patent: 6505317 (2003-01-01), Smith et al.
patent: 6651198 (2003-11-01), Wang
patent: 2003/0065997 (2003-04-01), Yamazaki et al.
patent: 2004/0177296 (2004-09-01), Saito

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