Built-in self-test for logic circuitry at memory array output

Details Built-in self-test for logic circuitry at memory array output Built-in self-test for logic circuitry at memory array output

1995-05-01

1996-09-03

Canney, Vincent P.

Excavating

371 223, G01R 3128

Patent

active

055530826

ABSTRACT:
Built-in self-testing of embedded logic circuitry at the output of an on-chip memory array is presented. Testing is accomplished by generating on chip a test pattern which is provided to the logic circuitry by writing at least a portion thereof into the memory array and then reading that portion out of the memory array, to the embedded logic circuitry. Three specific embodiments are presented, each of which employs a deterministic looping test pattern that comprises a portion of the generated test pattern. The looping test pattern may be either written through the memory array to the embedded logic circuitry or written around the memory array directly to the logic circuitry.

REFERENCES:
patent: 4404519 (1983-09-01), Westcott
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 5042034 (1991-08-01), Correale, Jr. et al.
patent: 5101409 (1992-03-01), Hack
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5172377 (1992-12-01), Robinson et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5260947 (1993-11-01), Posse
patent: 5442640 (1995-08-01), Bardell, Jr. et al.

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