Built-in self test for integrated circuits

Details Built-in self test for integrated circuits Built-in self test for integrated circuits

1990-08-31

1992-12-22

Canney, Vincent P.

Excavating

371 251, G06F 1100

Patent

active

051739062

ABSTRACT:
A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail
o-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

REFERENCES:
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4931722 (1990-06-01), Stoica
patent: 5006787 (1991-04-01), Katircioglu et al.
patent: 5051997 (1991-09-01), Sakashita et al.
patent: 5103167 (1992-04-01), Okano et al.

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