Built-in self test for integrated circuit memory

Details Built-in self test for integrated circuit memory Built-in self test for integrated circuit memory

1990-02-15

1992-08-11

Smith, Jerry

Excavating

371 225, 371 212, 371 27, G11C 2900

Patent

active

051386194

ABSTRACT:
In a built-in self test ("BIST") circuit for on-chip testing of an integrated circuit memory, a control logic circuit is responsive to an external signal on a test select pin for controlling the BIST operations of the major circuit groups thereof. The major circuit groups include an address PRPG (pseudo-random pattern generator), which selectively furnishes test addresses or mission addresses to the memory; a data PRPG, which selectively furnishes test data or mission data to the memory; a PSA (parallel signature analyzer) PRPG, which furnishes mission data from the memory in normal mode and determines a signature in test mode; and a decoder, which compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass/fail. The BIST circuit is modular and extendable for any N-word by M-bit memory. To this end, a counter in the control logic circuit comprises a plurality of counter slices, the address PRPG comprises a plurality of address slices, the data PRPG comprises a plurality of data slices, and the PSA PRPG comprises a plurality of PSA slices. The BIST circuit is formed by replicating slices for the major circuit groups. Only certain feedback paths in the major circuit groups and certain control signal combinatorial circuits in the control logic require customization.

REFERENCES:
patent: 4195770 (1980-04-01), Benton et al.
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4370746 (1983-01-01), Jones et al.
patent: 4433413 (1984-02-01), Fasang
patent: 4608683 (1986-08-01), Shigaki
patent: 4782487 (1988-11-01), Smelser
patent: 4783785 (1988-11-01), Hanta
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 4876685 (1989-10-01), Rich
patent: 4888772 (1989-12-01), Tanigawa
patent: 4903266 (1990-02-01), Hack
AT&T, Parameterized Macrocells Data Sheet, RAMS1AT, pp. 8-22-8-27.
AT&T, Parameterized Macrocells Data Sheet, RAMS1CT, pp. 8-36-8-41.
Abadir & Reghbati, "Functional testing of semiconductor random access memories," Computing Surveys, vol. 15, No. 3, Sep. 1983, pp. 118-139.
Electronic Engineering Times, "European Silicon Turns to Big Chip," Jan. 8, 1990.
Nadeau-Dostie et al., "A serial interfacing technique for built-in and external testing for embedded memories," IEEE Custom Integrated Circuits Conference, 1989, pp. 22.2.1-22.2.5.
National Semiconductor Corporation, ASIC Design Manual, No. 400010, Rev. 1, various pages.
National Semiconductor Corporation, CMOS Logic Databook, No. 400039, Rev. 1, pp. 3-142-3-146.
Scholz et al., "ASIC implementation of boundary-scan and built-in self-test (BIST)," Journal of Semicustom ICs, vol. 6, No. 4, pp. 30-37.

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