Built-in self test for a satellite demodulator

Demodulators – Phase shift keying or quadrature amplitude demodulator

Reexamination Certificate

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Details

C329S306000, C375S224000, C375S228000, C455S067700, C455S330000, C455S226100

Reexamination Certificate

active

06259314

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing of demodulators in data reception systems and, more particularly, to built-in testing of data demodulators in satellites independent of uplink characteristics.
2. Description of the Prior Art
Satellite data transmission systems are in wide spread usage. These systems suffer from an inability to determine the source of malfunctions within the data transmission uplink. While an erroneous data stream can be detected with a retransmission from a satellite which indicates a malfunction in the uplink, it is very difficult to determine the source of the malfunction from the ground in view of the inaccessibility of the satellite electronics for testing. Currently, determination of the source of a malfunction requires backtracking from the detection of erroneous data in a retransmission from the satellite with there being no current methodology by which the satellite onboard electronics in the data demodulator can be tested conveniently from the ground to determine if malfunctions exist in the demodulator.
FIG. 1
illustrates a block diagram of a conventional demodulator
10
of the type used in data transmission satellites. The demodulator
10
receives an input signal IF
in
which has been shifted down in frequency by the satellite to an intermediate frequency. The input signal IF
in
containing data is applied to an analog to digital converter
12
which digitizes the input signal IF
in
into an output containing a large number of samples which are inputted to a tuner
14
. The tuner
14
processes the digitized data outputted by the analog to digital converter
12
into quadrature signal processing paths
16
and
18
which each contain a frequency converter
20
which downwardly shifts the input signal IF
in
to a lower frequency. The frequency converters
20
of the I signal processing path
16
and the Q signal processing path
18
respectively receive input carriers COS(&ohgr;T) and SIN(&ohgr;T) from the quadrature digital sinewave generator which cause the frequency converters to produce the quadrature I and Q signals which were downshifted in frequency to a lower carrier frequency. The input to the quadrature digital sinewave generator
22
is a frequency command F
in
which commands the quadrature digital sinewave generator
22
to output the quadrature carriers COS(&ohgr;T) and SIN(&ohgr;T) of the appropriate frequency to cause the frequency converters to shift the input signal IF
in
to the lower carrier frequency for further signal processing. The envelopes of the lower frequency quadrature carriers produced by connection of COS(&ohgr;T) and SIN(&ohgr;T) to the frequency converters
20
are modulated with the quadrature components of data present in the intermediate frequency input signal IF
in
. The outputs from the frequency converters
20
are applied to suitable low pass filters
24
which attenuate frequency components outside the desired lower carrier frequency band to which the I and Q data components are shifted. The output I and Q signals are applied to downstream demodulator processing
26
of a conventional nature including channelization, discrete Fourier transformation (DFT) and other known signal processing techniques.
As has been stated above, a demodulator, including a tuner
14
in accordance with the prior art of
FIG. 1
, is not readily diagnosed for malfunctions occurring downstream of the tuner. This seriously affects the ability to locate where processing errors occur when the output transmissions of a data satellite contains erroneous data.
FIG. 2
illustrates a block diagram of a preferred embodiment of a demodulator containing a digital tuner
30
of the type used with the practice of the present invention. It should be understood that separate I and Q channels are present in
FIG. 2
but have been omitted to simplify the illustration. The digital tuner
30
receives an intermediate frequency data input IF
in
like that of
FIG. 1
which is applied to an analog to digital converter
32
which performs the same function as the analog to digital converter of
FIG. 1
to sample the data into a large number of data samples. The output of the analog to digital converter
32
contains an extremely high number of samples which are applied as an input to a Hilbert transform filter
34
of well-known construction. The Hilbert transform filter
34
performs two tasks which are to convert a real data input into a complex data output having real and imaginary components and to further greatly attenuate half of the wideband digital spectrum of the incoming digital signal. The output of the Hilbert transform filter
34
is applied to a frequency converter
36
which shifts the intermediate frequency input data after filtering by the Hilbert transform filter
34
to a lower carrier frequency. The inputting of digitally synthesized quadrature sinewaves from a digital frequency synthesizer
38
to the frequency converter
36
downwardly shifts the data in the same manner as described above in conjunction with FIG.
1
. The particular specified frequency down to which the data outputted from the Hilbert transfer filter
34
is shifted is specified by the input FREQUENCY CONTROL WORD
40
. As a consequence of the filtering function performed by the Hilbert transform filter
34
eliminating at least half the digital data bandwidth and by the frequency converter
36
downshifting the filtered data, the output from the frequency converter is applied to a down sampler
42
which eliminates the excess half of the data samples. The output of the down sampler is applied to a frequency shift
44
which shifts up the frequency of the output from the down sampler
42
by a frequency shift equal to one quarter of data sampling rate F
s
. A frequency shift controller
45
produces control signals SWITCH RAILS, NEGATE Q and NEGATE I which operate in accordance with the relationship set forth in the table below to produce a cyclical output of +1, +j, −1 and −j which is clocked at the data sampling rate F
s
. The circuitry for generating the control signals is discussed below in conjunction with FIG.
5
.
Multiplier
Control Signals
+1
do not negate, nor swap rails
+j
negate Q-rail, swap rails
(i.e. I and Q are switched)
−1
negate both rails, do not swap rails
−j
negate I-rail, swap rails
The frequency shift
44
outputs I and Q data signals which are shifted to a correct frequency position to align the I and Q data in frequency with channels to be produced by a channelizer within digital demodulator processing
46
in a manner like FIG.
1
.
For spectral efficiency and to prevent aliasing due to the down sampler
42
, the digital spectrum produced by the frequency conversion
36
has channels positively and negatively spaced about baseband but does not have a channel at baseband. A channelizer requires alignment of the input data with a channel centered at baseband in order to function properly. The frequency shift
44
performs a frequency shift equal to one quarter of the data sampling rate F
s
where F
s
is the data sample rate of data outputted from the down sampler
42
.
The demodulator containing the digital tuner
30
of
FIG. 2
, like the demodulator
10
of
FIG. 1
, suffers from not being readily testable for malfunctions of the demodulator signal processing downstream of the tuner from a remote location.
SUMMARY OF THE INVENTION
The present invention is a demodulator and a method of data reception and testing of a demodulator which permits remote testing of a demodulator in a data receiving device such as, but not limited to, a satellite. The invention permits testing of demodulator electronics independent of data input characteristics, such as uplink and downlink characteristics, in the satellite. The invention provides built-in self-testing of a demodulator by utilizing a locally generated test signal which is modulated at the tuner from baseband onto a carrier frequency which is injected at the tuner. The test signal output from

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