Built-in self-test flip-flop with asynchronous input

Details Built-in self-test flip-flop with asynchronous input Built-in self-test flip-flop with asynchronous input

1994-05-10

1995-05-16

Beausoliel, Jr., Robert W.

Excavating

371 223, H04B 1700

Patent

active

054167841

ABSTRACT:
A BIST cell having a memory element with an asynchronous input in a logic circuit using a built-in self-test mechanism. The BIST cell includes logic to provide a data signal to the memory element during user mode, a reset value to the memory element during reset mode, a scan signal value to the memory element during scan mode, and the sume of the data, reset and scan values during test mode. The BIST cell also prevents the memory element from being reset during test mode.

REFERENCES:
patent: 4669061 (1987-05-01), Bhavsar
patent: 4894830 (1990-01-01), Kawai
patent: 5006787 (1991-04-01), Katircioglu et al.
patent: 5027355 (1991-06-01), Stoica
patent: 5103167 (1992-04-01), Okano et al.

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