Built-in-self-test circuitry for testing a phase locked loop...

Details Built-in-self-test circuitry for testing a phase locked loop... Built-in-self-test circuitry for testing a phase locked loop...

2000-10-17

2001-09-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331S017000

Reexamination Certificate

active

06294935

ABSTRACT:

BACKGROUND
The present invention concerns circuit testing. More particularly, the present invention relates to built-in-self-test (BIST) circuitry for testing a phase locked loop (PLL) circuit.
Once manufactured, it is necessary to test very large scale integrated (VLSI) circuits to detect processing faults which could impair or inhibit correct operation of the circuit. Typically, this has been done by the external application of various test stimuli to inputs of the circuit and checking the actual response with an expected response.
As the complexity of some circuits increase, it is increasingly difficult to thoroughly test such circuits using just the external application of test stimuli. To facilitate testing of these more complex circuits, built-in self-test (BIST) circuitry is often included within the manufactured circuit to serve as an aid in the testing process. See for example, Edward J. McCluskey, Built-In-Self-Test Techniques,
IEEE Design & Test,
Volume 2, Number 2, April 1985, pages 21-28. See also, Edward J. McCluskey, Built-In Self-Test Structures,
IEEE Design
&
Test,
Volume 2, Number 2, April 1985, pages 29-36.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a built-in-self-test circuit aids in testing a phase locked loop circuit. The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit includes a frequency divider and a multiplexer. The frequency divider has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer selects its corresponding divide-by-counter to produce a test output clock.
In a specific preferred embodiment, the constant is ½. In this embodiment the plurality of frequency multipliers includes a six times frequency multiplier, a five times frequency multiplier, a four times frequency multiplier, a three times frequency multiplier and a two times frequency multiplier. The plurality of divide-by-counters includes a divide by twelve counter, a divide by ten counter, a divide by eight counter, a divide by six counter and a divide by four counter. Multiplier select lines are used by the PLL to select a frequency multiplier and by the multiplexer for selecting its corresponding divide-by-counter.
The present invention provides for efficient and accurate testing of a phased locked loop regardless of frequency multiplication performed by the phased locked loop.


REFERENCES:
patent: 5381085 (1995-01-01), Fischer
patent: 5729151 (1998-03-01), Zoerner et al.
patent: 6005904 (1999-12-01), Knapp et al.
patent: 6121816 (2000-09-01), Tonks et al.
patent: 6201448 (2001-03-01), Tam et al.
Edward J. McCluskey, Built-In Self-Test Techniques,IEEE Design&Test, vol. 2, No. 2, Apr. 1985, pp. 21-28.
Edward J. McCluskey, Built-In Self-Test Structures,IEEE Design&Test, vol. 2, No. 2, Apr. 1985, pp. 29-36.
“0.20-Micron VSC10PL01 Clock Distribution PLL”, Available from Philips Electronics North America Corporation, 1251 Avenue of the Americas, New York, New York 10020.

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