1992-12-15
1994-04-05
Beausoliel, Jr., Robert W.
Excavating
371 224, 371 251, H04B 1700
Patent
active
053011996
ABSTRACT:
A built-in self test circuit includes a pattern generator, a functional block subjected to a self test on the basis of an output from the pattern generator, a space compressor for compressing a test result of the functional block, and a comparator for comparing an output from the space compressor with an expected value and outputting a comparison result. The functional block has O (positive integer) inputs and M (positive integer) outputs. The pattern generator is constituted by a linear feedback shift register, having an output bit width P (P=O/N) which is 1/N of the inputs O of the functional block, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from the linear feedback shift register in units of N outputs and outputting, to the functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from the linear feedback shift register every P bits. The space compressor has a function of spatially compressing the M outputs from the functional block into L outputs (positive integer and M>L). The pattern generator, the functional block, the space compressor, and the comparator are built into a semiconductor chip into which other functional elements are built.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4670877 (1987-06-01), Nishibe
patent: 4847839 (1989-07-01), Hudson, Jr. et al.
patent: 4903266 (1990-02-01), Hack
patent: 5033048 (1991-07-01), Pierce et al.
patent: 5051996 (1991-09-01), Bergeson et al.
patent: 5051997 (1991-09-01), Sakashita et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5142222 (1992-08-01), Tamaka et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5184067 (1993-02-01), Nozuyama
patent: 5202978 (1993-05-01), Nozuyama
Implementing a Built-In Self-test PLA Design Robert Treuer, Hideo Fugiwara and Vinod K. Agarwal McGill University May 1985 pp. 37-48.
Patrick P. Gelsinger, "Design and Test of the 80386" published by IEEE Design & Test, Jun. 1987, pp. 42-50.
Sudhakar M. Reddy and et al., "A Data Compression Technique for Built-In Self-Test" published by IEEE Transactions on Computers, vol. 37, No. 9, Sep. 1988, pp. 1151-1156.
Laung-Terng Wang et al., "Linear Feedback Shift Register Design Using Cyclic Codes" published by IEEE Transactions on Computers, vol. 37, No. 10, Oct. 1988, pp. 1302-1306.
Ikenaga Takeshi
Takahashi Jun-Ichi
Beausoliel, Jr. Robert W.
De'cady Albert
Nippon Telegraph and Telephone Corporation
LandOfFree
Built-in self test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Built-in self test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Built-in self test circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-517856