Built-in self-test (BIST) circuit

Details Built-in self-test (BIST) circuit Built-in self-test (BIST) circuit

1991-04-25

1993-07-20

Beausoliel, Jr., Robert W.

Excavating

H04B 1700

Patent

active

052300005

ABSTRACT:
Testing of data path circuitry (12) within an integrated circuit chip (10) is accomplished by a test circuit (22) comprised of a Signature Analysis Register (SAR) (30). The SAR (30) generates test signals for input to data path circuitry (12) and compacts response signals produced by the data path circuitry following receipt of the test signals. A blocking circuit (28) blocks an initial one of the response signals from being received by the SAR (30) until the test signals from the SAR have propagated through the data path circuitry (12). Bypass multiplexers (34) multiplex the test signals generated by the SAR (30) with input data normally supplied to the data path circuitry (12) to allow the test circuit (22) to be bypassed during intervals other than testing. Loopback multiplexers (26) are also provided to multiplex the output data of the data path circuitry (12) with the input data received by the data path circuitry (12) to allow for testing of a chain of integrated circuits (10 ) on a circuit board (53).

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"An Automated BIST Approach for General Sequential Logic Synthesis", C. E. Stroud, 25th ACM/IEEE Design Automation Conference, 1988, Paper 3.1, pp. 3-8.
"Circular BIST with Partial Scan," M. M. Pradhan, E. J. O'Brien, S. L. Lam, and J. Beausang, Proceedings, IEEE 1988 International Test Conference, Paper 35.1, pp. 719-729.

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