Built-in parallel testing circuit for use in a processor

Details Built-in parallel testing circuit for use in a processor Built-in parallel testing circuit for use in a processor

1985-12-17

1987-08-18

Fleming, Michael R.

Excavating

324 73R, G01R 3128

Patent

active

046882227

ABSTRACT:
The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the form of shift register means for the shift clock controlled application of test data and for receiving result data, and which comprise means (58) for comparing the actual result data with desired result data, said means setting an error indicator (59) for initiating further actions in the case of a mismatch. For testing the correct implementation of operations and operational secondary functions, a signature generator circuit (30) is provided comprising a test accumulator (51, 52, . . . , 5m) for accumulating the test and result data from the storage elements (23, 24) and a test clock generator and counter (28) for controlling the accumulation, as well as a test memory (29) providing test programs consisting of test data, desired result data and instructions to be tested of the processor instruction set. The signature generator circuit ( 30) is connected to an interface register (11, 12, . . . , 1m) and/or a system bus (8) of the processor, the stages of the interface register being included in the shift register means consisting of the storage elements (23, 24) at positions 21, 22, . . . , nm.

REFERENCES:
patent: 4476431 (1984-10-01), Blum
patent: 4498172 (1985-02-01), Bhausar
patent: 4517672 (1985-05-01), Pfleiderer
patent: 4534028 (1985-08-01), Trischler
patent: 4553236 (1985-11-01), Zasio
patent: 4554664 (1985-11-01), Schultz

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