Built-in jitter measurement circuit

Details Built-in jitter measurement circuit Built-in jitter measurement circuit

2011-03-22

2011-03-22

Flores, Leon (Department: 2611)

Pulse or digital communications

Synchronizers

C375S355000, C375S371000, C375S373000, C375S376000, C327S141000, C327S147000, C327S156000, C455S260000, C455S516000

Reexamination Certificate

active

07912166

ABSTRACT:
A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

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Jui-Jer Huang et al., “An Infrastructure IP for On-Chip Clock Jitter Measurement” IEEE Computer Society, Proceedings of the IEEE International Conference on Computer Design, 2004.
Stephen Sunter et al., “ BIST for Phase-Locked Loops in Digitals Applications” ITC International Test Conference, 1999 IEEE, pp. 532-539.

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