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G06F 1100

Patent

active

058449167

ABSTRACT:
A method of testing an integrated circuit chip comprised of applying to and storing a first test pattern of data on the chip, applying a second test pattern of data to the chip which corresponds to the first test pattern, comparing the stored test pattern with the second test pattern on the chip, and indicating a test fault on a test pad in the event at least one bit of the first and second test pattern differ from each other.

REFERENCES:
patent: 5619513 (1997-04-01), Shatter et al.
patent: 5659553 (1997-08-01), Suzuki

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