Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-09-29
2002-07-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S208000, C327S214000, C327S333000, C326S081000, C326S083000
Reexamination Certificate
active
06426658
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to buffer circuits. More particularly, the present invention relates to buffer circuits that are capable of receiving and producing reduced voltage signals.
BACKGROUND OF THE INVENTION
Buffer circuits are typically employed in integrated circuits (ICs). In conventional buffer circuits, the upper power rail is at V
DD
and the lower power rail at ground. V
DD
is the voltage level at which the majority of the logic in the IC operate. The input and output signals of the buffer circuit swing between 0V (for a logic 0) and V
DD
(for a logic 1).
The power consumption of the IC is related to the value of V
DD
. Power consumption, in some instances, is a concern for IC designers. For example, it is desirable to design ICs which consume less power for portable applications, thereby enabling longer operation without recharging. Thus, it is desirable to provide a buffer circuit which decreases power consumption.
SUMMARY OF THE INVENTION
The invention relates to a buffer circuit that receives and generates signals having a reduced voltage range from V
SS
to V
RED
. In accordance with the invention, V
RED
comprises a voltage level less than V
DD
, where V
DD
is the voltage used to operate a majority of the logic in the integrated circuit, V
DD
is about 3.3 volts or less. In one embodiment, the buffer circuit comprises input and output stages. The output stage comprises pull-up and pull-down transistors coupled in series between V
RED
and V
SS
. The output node is coupled between common terminals of the pull-up and pull-down transistors. The pull-up and pull-down transistors operate in a push-pull configuration. When the pull-up transistor is switched on and the pull-down transistor is switched off, the output stage generates a logic 1 output signal equal to about V
RED
. On the other hand, when the pull-up transistor is switched off and the pull-down transistor is switched on, the output stage generates a logic 0 output signal equal to about V
SS
.
REFERENCES:
patent: 5367205 (1994-11-01), Powell
patent: 5461585 (1995-10-01), Chonan
patent: 5559452 (1996-09-01), Saito
patent: 6163171 (2000-12-01), Jinbo
patent: 6271713 (2001-08-01), Krishnamurthy
Hanson David Russell
Mueller Gerhard
Braden Stanton
Englund Terry L.
Infineon - Technologies AG
LandOfFree
Buffers with reduced voltage input/output signals does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buffers with reduced voltage input/output signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffers with reduced voltage input/output signals will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2821196