Buffering for LC-based stage

Details Buffering for LC-based stage Buffering for LC-based stage

2001-08-09

2003-02-25

Le, Don (Department: 2819)

Oscillators

Ring oscillators

C331S105000, C331S10800D, C327S280000, C327S281000

Reexamination Certificate

active

06525617

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to control of phase shift for a ring oscillator.
BACKGROUND OF THE INVENTION
A conventional approach for an LC-based ring oscillator uses three LC stages, with a phase shift sum for the three stages being 180°, as required to support an oscillation. Use of three or four stages is necessary with a conventional approach, because any stage provides a phase shift of less than 90°, except at certain extreme or unrealistic choices of parameter values. In the simplest three-stage oscillator, each stage provides 60° of phase shift. This arrangement is not suitable for applications that require in-phase and quadrature clock signals that are spaced 90° apart. Some workers have attempted to handle this problem by providing a four-stage ring oscillator in which each stage provides a 45° phase shift. See, for example, J. Savoj and B Razavi, “A 10 GB/s CMOS Clock and Data recovery Circuit with Frequency Detection”, 2001 I.E.E.E. International Solid State Circuits Conference Digest, Technical Paper No. 5.3.
What is needed is an LC-based ring oscillator configuration that provides 90°, or preferably more, phase shift in each of two stages so that in-phase and quadrature signals, including but not limited to clock signals, can be generated using output signals from two successive stages of the oscillator.
SUMMARY OF THE INVENTION
These needs are met by the invention, which uses selected signal buffers plus selected LC circuits to provide additional phase shift in each stage so that, optionally, each stage can provide a 90° phase shift without using extreme values to attain this. The additional phase shift is provided by two in-line buffers, incorporated in the forward path, each providing an additional phase shift (estimated to be 0-30°, depending upon the configuration used).


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Jafar Savoj, et al., “A 10Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection”, 2001 IEEE International Solid-State Circuits Conference, ISSCC 2001/Session 5/Gigabit Optical Communications I/5.3, pp. 78-79. Feb. 2001.

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