Buffered routing element for a user programmable logic device

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307465, 307468, 307243, H03K 19017

Patent

active

048556190

ABSTRACT:
A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

REFERENCES:
patent: 4371797 (1983-02-01), Frank
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patent: 4642487 (1987-02-01), Carter
patent: 4709173 (1987-11-01), Nishimichi et al.
patent: 4758745 (1988-07-01), Elgamal et al.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct, 1980, pp. 220-233.

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