Buffered-layer memory cell

Details Buffered-layer memory cell Buffered-layer memory cell

2006-04-18

2006-04-18

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

Reexamination Certificate

active

07029924

ABSTRACT:
A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X(YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3(PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

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patent: 2004/0235309 (2004-11-01), Hsu
patent: 2004/0256697 (2004-12-01), Jang

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