Buffered FET logic gate using depletion-mode MESFET's.

Details Buffered FET logic gate using depletion-mode MESFET's. Buffered FET logic gate using depletion-mode MESFET's.

1986-11-13

1987-12-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307443, 307475, H03K 19017, H03K 19094

Patent

active

047120231

ABSTRACT:
A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (V.sub.I); and thereby a high load drivability with a low power consumption rate is realized.

REFERENCES:
patent: 4177390 (1979-12-01), Cappon
patent: 4423339 (1983-12-01), Seelbach et al.
patent: 4450369 (1984-05-01), Schuermeyer
Deming et al., "GaAs Configurable Cell Array Using BFL", IEEE JSSC, vol. SC-19, No. 5, Oct. 1984, pp. 728-737.
Livingstone et al., "Capacitor Coupling GaAs FET's", IEE Proc, Vol. 127, Pt. I, No. 5, Oct. 1980, pp. 297-300.
"Design and Fabrication of Depletion GaAs LSI High-Speed 32-Bit Adder", Yamamoto et al, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.

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