Buffer system using parity checking of address counter bit for d

Details Buffer system using parity checking of address counter bit for d Buffer system using parity checking of address counter bit for d

1984-12-24

1987-09-08

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 49, 371 50, 371 51, G06F 1110

Patent

active

046928936

ABSTRACT:
A data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n+1 bits. The n+1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n+1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n+1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An errror is signaled if the n+1th bit of the read address counter does not agree with the n+1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read. The same entries on a next pass through the array.

REFERENCES:
patent: 3836891 (1974-09-01), McDaniel
patent: 4092522 (1978-05-01), Miller
patent: 4271521 (1981-06-01), Mahmood
patent: 4360917 (1982-11-01), Sindelar et al.
patent: 4365332 (1982-12-01), Rice
"Buffer Memory with Detection of Data Errors and Errors Caused by Faults in the Read and Write Address Registers" by D. M. Duffy, W. R. Lockwood and T. K. Zimmerman, Research Disclosure, Jan. 1986, No. 261, A-132, Kenneth Mason Publications Ltd, England.

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