Boots – shoes – and leggings
Patent
1982-09-30
1986-08-05
Chan, Eddie P.
Boots, shoes, and leggings
3408255, G06F 1318, G06F 1300
Patent
active
046046828
ABSTRACT:
A buffer system for interfacing an intermittently accessing data processor to a communications system in which the transfer of data bits is clocked at a predetermined rate in response to clock pulses provided by a communications system clock signal. The system includes a random access memory (RAM) for storing input signal data bytes received from an input communications channel of the communications system and for storing output signal data bytes for transmission to an output communications channel of the communications system; and a port interface section that is responsive to the system clock signal for serially receiving and transmitting input signal data bytes from the input channel, for storing output signal data bytes to the output channel and for providing a flag signal to demarcate the data bytes. A transfer control signal generator responds to the flag signal by generating a sequence of transfer control signals for causing the RAM to store input signal data bytes from the port interface section, for enabling output signal data bytes stored in the RAM to be transferred to the port interface section, and for terminating the flag signal. The transfer control signal generator is adapted to respond to preemption signals provided while the RAM is accessed by the data processor by interrupting its sequential generation of transfer control signals during the interval of the preemption signal and to respond to the termination of the preemption signal by resuming said sequential generation of transfer control signals at the point of interruption.
REFERENCES:
patent: 3588825 (1971-06-01), Shook et al.
patent: 3636525 (1972-01-01), Inaba et al.
patent: 3641326 (1972-02-01), Harte
patent: 3668653 (1972-06-01), Fair et al.
patent: 3876984 (1975-04-01), Chertok
patent: 3883851 (1975-05-01), Drake et al.
patent: 4068297 (1978-01-01), Komiya
patent: 4069488 (1978-01-01), Fiorenza et al.
patent: 4100597 (1978-07-01), Fleming et al.
patent: 4104731 (1978-08-01), Grudowski
patent: 4109309 (1978-08-01), Johnstone et al.
patent: 4121284 (1978-10-01), Hyatt
patent: 4122519 (1978-10-01), Bielawski et al.
patent: 4132981 (1979-01-01), White
patent: 4150326 (1979-04-01), Engelberger et al.
patent: 4162519 (1979-07-01), Hanewinkel
patent: 4209840 (1980-06-01), Beradi et al.
patent: 4257095 (1981-03-01), Nadir
patent: 4271518 (1981-06-01), Birzele
patent: 4275457 (1981-06-01), Leighou et al.
patent: 4527233 (1985-07-01), Ambrosius, III et al.
Schwan Eduard A.
Schwan Herbert A.
Callan Edward W.
Chan Eddie P.
Teleplex Corporation
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