Buffer storage system

Details Buffer storage system Buffer storage system

1984-12-05

1987-12-15

Eng, David Y.

Boots, shoes, and leggings

G06F 936

Patent

active

047137525

ABSTRACT:
A buffer storage system for a pipeline processor, set up with at least an operand access buffer storage and an instruction fetch buffer storage. The buffer storages cooperate with store address registers and store data registers, to assume a store-through method between the buffer storages and a main storage. A feedback means is mounted between the buffer registers and the store address/data registers. This feedback means is activated during an operand store operation to apply an operand store address and an operand store data, from the store address and store data registers, to the instruction fetch buffer register for effecting coincidence in data among the storages.

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patent: 4551797 (1985-11-01), Amdahl
patent: 4551799 (1985-11-01), Ryan et al.
patent: 4583163 (1986-04-01), Kobayashi et al.
Electronics International, vol. 55, No. 16, Aug. 1982, pp. 112-117, New York, U.S.; P. Knudsen: "Supermini Goes Multiprocessor Route to Put It Up Front in Performance", p. 113, right-hand column, lines 23-33; p. 116, right-hand column, lines 11-26; p. 117, figure: For a Write Operation.
Computer Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530, New York, A. J. Smith: "Cache Memories", p. 503, right-hand column, line 49-p. 55, left-hand column.
IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 262-263, New York, F. T. Blount et al.: "Deferred Cache Storing Method."

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