Buffer storage control method and apparatus

Details Buffer storage control method and apparatus Buffer storage control method and apparatus

1990-05-17

1992-08-04

Fleming, Michael R.

Boots, shoes, and leggings

3642397, 3642564, 3642565, 3642602, 3649632, 3649571, G06F 900, G06F 1500

Patent

active

051367025

ABSTRACT:
An information processing system includes a processor, a main storage, a buffer storage for holding a copy of a part of data of the main storage, an address translator for translating a logical address composed of a page address portion and an address portion within the page into a real address and a system controller and a buffer storage control unit. The buffer storage control unit includes a first detector and a second detector. The first detector detects presence or absence of a requested data in the buffer storage by using the real address obtained from making access to the buffer address array portion by using N bits of a part of the page address portion and the address portion within the page, and the real address obtained from the address translator and the second detector includes at least one address holding register for storing a real address of which data is not held in the buffer storage and detects presence or absence of the requested data in the buffer storage by using the contents of the address holding register and the real address obtained from the address translator in parallel with making access to the buffer address array portion.

REFERENCES:
patent: 3902163 (1975-08-01), Amdahl et al.
patent: 4700291 (1987-10-01), Saito
patent: 4779193 (1988-10-01), Koga et al.
patent: 4803616 (1989-02-01), Uchiyama et al.
patent: 4890220 (1989-12-01), Nakagawa et al.

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