Buffer queue write pointer control circuit notably for self-chan

Details Buffer queue write pointer control circuit notably for self-chan Buffer queue write pointer control circuit notably for self-chan

1988-12-21

1990-06-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04J 302, H04J 326

Patent

active

049339320

ABSTRACT:
The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.

REFERENCES:
patent: 4603416 (1986-07-01), Servel et al.
patent: 4646294 (1987-02-01), Eliscu et al.
patent: 4799219 (1989-01-01), Calvignac et al.

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