Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-05-22
2001-05-29
Ton, Dang (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06240095
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
BACKGROUND OF THE INVENTION
In the communication of electronic signals over networks, for example the Internet, or between high speed computers, it is often necessary to provide a buffer memory interface that provides short term storage of data being received prior to transmission of that data. The storage may be necessary to accommodate different communication protocols for the received and transmitted data, such as may include an underlying difference in data transmission rate, or may simply result from the asynchronous operation of the interconnected network and host devices.
Such buffer memory interfaces present a bottleneck to the rapid transfer of data so there is considerable interest in speeding the progress of data through the buffer memory.
In this regard, it is known to make use of a dual port random access memory (DPRAM) that permits simultaneous writing to and reading from the buffer memory of the interface as opposed to a sharing of a single set of data and address lines per conventional computer memory.
A buffer memory interface using a DPRAM may include two specialized interface circuits operating under the control of a dedicated microprocessor. The interface circuits handle the low-level protocols of communicating with the network and host devices joined by the buffer memory interface.
Many sophisticated high speed data transmission protocols transmit data in packets each containing a header identifying the packet to a longer message. Packetization of the data allows resources along the network to be pre-allocated to provide space for the receipt of the data and allow the media along which the data is transmitted to be more easily shared or multiplexed between different messages and packets. The header information allows the packets to be reassembled even if they don't arrive continuously or even in order.
For the receipt of packet data from a network, using a buffer memory interface, the microprocessor causes the network interface circuit of the buffer memory interface to issue a credit to the network device for a small amount of data—typically less than a full packet. According to a pre-established protocol, the network device then sends a data burst to the buffer memory interface, the burst including the header for a packet. This header is read by the microprocessor to determine the size of the packet and enough additional credits are issued to allow the entire packet to be received. The network interface circuit then handles the transfer of the data into the buffer memory for the number of credits issued after which time it interrupts the microprocessor. The microprocessor reads the word count collected by the interface circuit and moves a pointer in the DPRAM to be ready for the next packet. This process is repeated for each packet.
For the transmission of a packet of data from the host device to the network, the microprocessor first establishes a connection to the network device. It then calculates an address for the data on the network and sets a word count in a register of the network interface circuit. The network interface circuit then proceeds to transmit the data to the network device until the word count has been transmitted at which time it interrupts the microprocessor to set up a new transmission.
By using the microprocessor interrupt capabilities, the microprocessor coordinates its operation with the network and host interface circuits. Nevertheless the interrupt process is relatively inefficient requiring many machine cycles of the microprocessor during which time the data of the interrupted microprocessor task is saved and a new task for the interrupt is loaded. Importantly, as the present inventors have recognized, during the interrupt process the host or network interface circuits remain idle awaiting instructions from the microprocessor.
However, the use of a microprocessor provides great flexibility in the operation of the buffer memory interface, allowing it to be reprogrammed for use in different situations. In contrast, the interface circuits are usually realized as programmable array logic (PALs) providing for high speed operation, but limited reprogramming capability.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a buffer memory interface having two levels of buffering, the first for the data being transmitted, as is conventional, and the second for instructions relevant to the interface circuits such as are exchanged with the microprocessor.
Generally, the network interface circuit handles the preliminary steps of receiving data by issuing as many credits as there is buffer memory available to the network device. Instructions to the microprocessor about the data subsequently received are placed in a receive buffer for later access by the microprocessor. Conversely, the microprocessor provides instructions to the network interface circuit via a command buffer. The network interface circuit reads the command buffer when it has concluded each transfer without interrupting the microprocessor.
As a result, the microprocessor may operate wholly asynchronously with the network interface circuitry, reading the receive buffer to determine if additional data has been received without being interrupted, and writing commands to the command buffer as necessary without the need for network interface circuit to interrupt it to indicate that it is ready for more data. The flexibility of a microprocessor-based interface is retained, yet the time consuming interrupt process used to synchronize the various portions of the interface is eliminated. There is very little idle time imposed on the network interface circuit.
Specifically, the buffer memory interface circuit may include an input buffer memory and a receive buffer memory. In this case a network interface circuit receives data from the network device according to an input transmission protocol and writes the data to the input buffer memory and writes instructions to the receive buffer related to the received data. The microprocessor reads instructions from the receive buffer and in response to those instructions causes a host interface circuit to read data from the input buffer memory for transmission to the host device according to a host transmission protocol.
Thus it is one object of the invention to allow more independence in the operation of the microprocessor and the network interface circuit thereby eliminating the need for interrupt-type linkage. The network interface circuit may be kept fully utilized by allowing it to work ahead of the microprocessor placing instructions to the microprocessor in the receive buffer memory. By allowing the network interface circuit and microprocessor more freedom to work independently, the network interface circuit may be operated essentially continuously so long as the microprocessor is able to keep up in its transfer of the data out of the input buffer memory. Idling of the network interface circuit during an interrupt process is wholly eliminated.
Alternatively or in addition, the microprocessor may write data received from the host device in an input transmission protocol to the output buffer memory and write transmission instructions to the command buffer memory related to the data. The network interface circuit may read the instructions from the command buffer and in response to those instructions, read data from the output buffer and transmits that data to the network device according to a host transmission protocol.
Thus it is another object of the invention to provide the same benefits as those described above with respect to the transmission of data from the host to the network. Should the command buffer memory be filled, the microprocessor may momentarily halt operation without slowing the data being transmitted by the network interface circuit. This is in contrast to the prior art in which the network interface circuit was required to wait during an interrupt operation for the microprocessor to provide it with more commands.
The foregoing and other objects
Beine Lawrence E.
Good Christopher J.
Genroco, Inc.
Quarles & Brady LLP
Sam Phirin
Ton Dang
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