Buffer memory subsystem for peripheral controllers

Details Buffer memory subsystem for peripheral controllers Buffer memory subsystem for peripheral controllers

1988-09-09

1993-08-24

Lall, Parshotam S.

Boots, shoes, and leggings

3642383, 3642426, 3642568, 364DIG1, G06F 900, G06F 1200

Patent

active

052396363

ABSTRACT:
A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.

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patent: 4593324 (1986-06-01), Ohkubo et al.
patent: 4604683 (1986-08-01), Russ et al.
patent: 4875154 (1989-10-01), Mitchell
Beukema et al., "Transparent Mode in an I/O Controller," IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 5956-5959.

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