Buffer memory management with register list to provide an ordere

Details Buffer memory management with register list to provide an ordere Buffer memory management with register list to provide an ordere

1993-11-02

1996-07-23

Swann, Tod R.

Boots, shoes, and leggings

395250, 364DIG1, G06F 1202, G06F 1208

Patent

active

055398979

ABSTRACT:
A buffer memory having addressable locations into which data blocks received from one of two or more devices are written and from which those data blocks are read to one of the other devices, is managed by a buffer memory controller. Selected, not necessarily sequential, buffer addresses are assigned by the controller to store data blocks included in a series supplied from the first device, and these assigned buffer addresses are loaded into register locations of a list register. Buffer addresses are read from an ordered list of the loaded register locations and respective data blocks are written into such addresses. Register locations from the ordered list are accessed to retrieve buffer addresses therefrom, and the data blocks stored in the retrieved buffer addresses are read from the buffer memory to the second device.

REFERENCES:
patent: 4065810 (1977-12-01), Cramer et al.
patent: 4866601 (1989-09-01), Dulac et al.
patent: 4876642 (1989-10-01), Gibson
patent: 5072369 (1991-12-01), Theus et al.
patent: 5083269 (1992-02-01), Syobatake et al.

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