Buffer memory for synchronizing data transmission and reception

Details Buffer memory for synchronizing data transmission and reception Buffer memory for synchronizing data transmission and reception

1992-02-21

1993-05-04

Shaw, Gareth D.

Boots, shoes, and leggings

395200, 395275, 364DIG1, 3642391, 3642393, G06F 1320, G06F 1342

Patent

active

052089134

ABSTRACT:
A digital audio tape recorder memory or a DAT memory includes a buffer memory for absorbing the operating speed difference between the computer and the DAT memory, and a control circuit for controlling the buffer memory. This buffer memory includes a plurality of addressable sections. The control circuit causes the input and output data to and from the computer to be written into and read out from the buffer memory to synchronize the transmission and reception between the two devices. The addressing of the buffer memory by the control circuit is controlled from section to section to simplify the control circuit.

REFERENCES:
patent: 4873703 (1989-10-01), Crandall et al.
patent: 4875224 (1989-10-01), Simpson
patent: 4890254 (1989-12-01), Cooley

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