Buffer memory device for packet data and method of controlling t

Details Buffer memory device for packet data and method of controlling t Buffer memory device for packet data and method of controlling t

1989-10-25

1991-05-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 856, 3408255, 34082551, H04J 324

Patent

active

050162489

ABSTRACT:
A buffer memory device and method for fixed-length packet data. The write and read addresses of a memory are controlled by respectively independent pointer queues and these pointer queues are arranged to be distributed to the address data queue of any of the packet queues. When data are concentrated on a specific packet queue, the address data of packet queues low in use frequently are distributed so that the writable area of the specific packet queue can be expanded.

REFERENCES:
patent: 4603416 (1986-07-01), Servel et al.
patent: 4707693 (1987-11-01), Hessel
patent: 4849968 (1989-07-01), Turner
patent: 4864495 (1989-09-01), Inaba
patent: 4864560 (1989-09-01), Quinquis et al.
patent: 4890226 (1989-12-01), Itoh

Affiliated with

Also associated with

Rating

Buffer memory device for packet data and method of controlling t does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Buffer memory device for packet data and method of controlling t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer memory device for packet data and method of controlling t will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1654388