Buffer memory data flow controller

Details Buffer memory data flow controller Buffer memory data flow controller

1993-02-19

1993-09-28

Richardson, Robert L.

395275, G06F 1300

Patent

active

052492710

ABSTRACT:
A data flow control system for regulating the flow of data through a buffer memory in a data storage system controller. The data flow controller system includes an up-down counter that is decremented for every byte of data that is placed into the controller's buffer memory, and incremented for every byte of data that is taken out of the buffer memory. The counter is preset to an initial value that represents the minimum amount of data that must be in the buffer memory before that data can be released to the storage system or to the computer interface, thereby permitting validation of the data prior to release. The value of the counter represents the amount of data that is in the buffer memory less the initial offset value. Detector circuitry coupled to the counter enables or disables the storage system or the computer interface depending upon the validity of the data in the buffer memory and the operational status of the storage system and the computer interface. An additional feature of the invention permits using the buffer memory as a cache for data read from the storage system. Intermediate status information about the buffer memory is generated in order to permit the storage system controller microprocessor to anticipate operational states, and improve data transfer efficiency. By directly controlling the data flow through the buffer memory, the storage system controller microprocessor is not directly involved in all aspects of data transfers, and therefore it is not required to operate at the higher speeds necessary with present day and future storage systems.

REFERENCES:
patent: 4258418 (1981-03-01), Heath
patent: 5136582 (1992-08-01), Firoozmand

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