Buffer memory control circuit for label scanning system

Details Buffer memory control circuit for label scanning system Buffer memory control circuit for label scanning system

1979-11-29

1982-08-10

Thesz, Joseph M.

Boots, shoes, and leggings

235 92DP, 235436, 3401463Z, G06F 728

Patent

active

043441521

ABSTRACT:
A scanning system includes a pair of buffer memories for alternately accumulating strings of signals which may contain bar coded label data. Candidate selection logic circuits examine incoming signals to generate a candidate signal when a string of signals satisfies gross logical tests. A control counter responds to the incoming signals and to the candidate signal to select an alternate buffer memory only when the active memory is fully loaded and contains at least part of a label candidate. The contents of the fully loaded memory are transferred to a processor for further analysis while incoming signals are routed to the alternate memory.

REFERENCES:
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patent: 3909787 (1975-09-01), Laurer et al.
patent: 4086477 (1978-04-01), Cowardin et al.
patent: 4147295 (1979-04-01), Nojiri et al.
patent: 4298954 (1981-11-01), Bigelow et al.
L'Onde Electrique, vol. 44, No. 446, pp. 535-543, May 1964, "Analyseur Multiparametrique".
Datamatron, vol. 6, No. 1, pp. 8-14, Jan./Feb. 1960, "The RW-100-A New Polymorphic Data System".

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