Buffer management for merging packets of virtual circuits

Details Buffer management for merging packets of virtual circuits Buffer management for merging packets of virtual circuits

2007-02-13

2007-02-13

Kizou, Hassan (Department: 2616)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S397000, C370S395410, C370S412000

Reexamination Certificate

active

10131577

ABSTRACT:
In one embodiment, an apparatus for coordinating merging of packets for one or more virtual circuits (VGs). Each packet of a VC comprising a sequence of cells terminates with an end of packet (EOP) cell. The apparatus comprises one or more buffers, a buffer controller, and a merge processor. Each buffer is configured to receive cells of an associated VC and a threshold value based on traffic of the VC. When a number of cells of a packet in a buffer exceeds the corresponding dynamic threshold value, a corresponding flag of the buffer is set. The buffer controller is configured to drop all cells of the current packet in response to a set flag of a corresponding buffer. The merge processor services each buffer in accordance with a scheduling method to transfer one or more packets from each buffer to an output packet stream.

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