Buffer layer for improving control of layer thickness

Details Buffer layer for improving control of layer thickness Buffer layer for improving control of layer thickness

1997-09-26

2000-01-11

Chaudhari, Chandra

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257622, 438296, 438763, 438970, 216 39, H01L 2900, H01L 2906, H01L 21336, H01L 2131, H01L 21469

Patent

active

060139374

ABSTRACT:
A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

REFERENCES:
patent: 5597756 (1997-01-01), Fazan
patent: 5656535 (1997-08-01), Ho
patent: 5763932 (1998-06-01), Pan

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