Buffer for driving capacitive load

Details Buffer for driving capacitive load Buffer for driving capacitive load

2011-06-21

2011-06-21

Wilson, Robert W (Department: 2475)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C455S313000, C455S259000, C455S326000, C455S334000, C327S065000, C327S112000, C327S118000, C327S127000

Reexamination Certificate

active

07965728

ABSTRACT:
A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

REFERENCES:
patent: 4802127 (1989-01-01), Akaogi et al.
patent: 5995819 (1999-11-01), Yamaji et al.
patent: 6278294 (2001-08-01), Taniguchi
patent: 2003/0013428 (2003-01-01), Marques et al.
patent: 2005/0186935 (2005-08-01), Kawama et al.
patent: 2007/0010228 (2007-01-01), Schelmbauer et al.

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