Buffer device with dual supply voltage for low supply...

Details Buffer device with dual supply voltage for low supply... Buffer device with dual supply voltage for low supply...

2000-12-13

2001-11-20

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S311000, C326S081000, C327S543000

Reexamination Certificate

active

06320361

ABSTRACT:

TECHNICAL FIELD
This invention relates to a buffer device with dual supply voltage for low supply voltage applications.
Specifically, the invention relates to an output buffer device having first and second supply voltage references, said first voltage reference being lower in value than said second voltage reference, of the type which comprises at least first and second complementary MOS transistors, which transistors are connected in series together between one of said supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of said buffer device, and have drain terminals connected together and to an output terminal of the buffer device.
The invention relates, particularly but not exclusively, to an output buffer device with dual supply voltage, and this description will cover that field of application for convenience of illustration only.
BACKGROUND OF THE INVENTION
As is well known, an abiding demand exists from the trade for semiconductor devices that can be operated at increasingly low supply voltages and large bandwidths.
The output buffers are a major design constraint in such devices. The desire is that such buffers output data at a very high rate despite being supplied a reduced voltage.
The problems encountered in the design of output buffer devices are intensified particular with devices that have a low internal supply voltage, while the supply voltage to the output buffers is still lower.
Shown schematically in
FIG. 1
is a typical structure of an output buffer device
1
. In particular, the output buffer device
1
comprises a complementary pair of CMOS transistors M
1
, M
2
which are connected in series together between a supply voltage reference Vcc and a second voltage reference, specifically a ground reference GND, and have control terminals connected together and to an input terminal IN of the output buffer device
1
, the latter being a voltage input signal Vin.
The passage from a logic low to a logic high, referred to as a low/high transition, of an output voltage signal Vpad at an output terminal PAD is effected in two steps, as specified herein below. 1. When Vpad<|Vtp|, the PMOS transistor M
1
is in a saturated condition, and the charge current Ic which raises the value of the voltage Vpad at the output terminal PAD is constant and given approximately as:
Ic
=
Kp
⁡
(
Vcc
+
Vtp
)
2
2
⁢
 
⁢
Zp
(
1
)
where:
Kp=&mgr;·Cox,
1/Zp=W/L (geometric parameters of PMOS transistor M
1
),
Vtp is the threshold voltage of PMOS transistor M
1
,
&mgr; is the electron mobility, and
Cox is the capacitance of the silicon layer of the transistors.
2. When Vpad>|Vtp|, the PMOS transistor M
1
is in the triode range, and the charge current Ic is dependent on the voltage Vpad presented at the output terminal PAD, it being given as:
Ic
=
Kp
⁡
(
Vcc
/
2
+
Vtp
+
Vpad
/
2
)
⁢
(
Vcc
-
Vpad
)
Zp
(
2
)
It appears from formulae (1) and (2) above that the charge current Ic is “quadratically” proportional to the supply voltage Vcc. With low supply voltages, large geometries (small values of Zp) must be used to provide the required fast transfer of the output data.
A state-of-art buffer device is disclosed for a supply voltage of 1.5V in U.S. Pat. No. 5,903,500 to Tsang et al. This document is related in particular to flash memories, and describes a high-speed output buffer device, which comprises a high-transconductance NMOS transistor suitably doped to have a lower threshold voltage than the threshold voltage of standard NMOS transistors.
The underlying technical problem of this invention is to provide an output buffer device for low supply voltage devices, which has such structural and functional features that it can overcome the constraints of comparable prior devices.
SUMMARY OF THE INVENTION
One embodiment of this invention uses an internal supply voltage reference of the buffer device to provide an optional path toward the output terminal, which would be selected by a control signal being issued from sensing circuitry.
The sensing circuitry monitors the input and output terminals of the buffer. When the input terminal begins a transition from one logic state to another, the sensing circuitry opens a current path from the internal supply voltage reference to the output terminal, providing additional current to the output terminal, reducing the charge time of the buffer circuit.
The features and advantages of a buffer device according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.


REFERENCES:
patent: 5105104 (1992-04-01), Eisele et al.
patent: 5903500 (1999-05-01), Tsang et al.
patent: 6060910 (2000-05-01), Inui
patent: 6069496 (2000-05-01), Perez
patent: 6078195 (2000-06-01), Chen

Affiliated with

Also associated with

Rating

Buffer device with dual supply voltage for low supply... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Buffer device with dual supply voltage for low supply..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer device with dual supply voltage for low supply... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2578888