Buffer device suitable for asynchronous transfer mode communicat

Details Buffer device suitable for asynchronous transfer mode communicat Buffer device suitable for asynchronous transfer mode communicat

1990-01-08

1992-01-21

Bowlep, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36518905, 36518912, 365221, 364DIG1, G06F 300, G06F 736, G11C 700

Patent

active

050832697

ABSTRACT:
A buffer device capable of dealing with multiple priority levels in which the efficiency of the memory capacity utilization can be improved such that the priority levels can be handled at the higher efficiency with smaller memory capacities, and which is adaptable to a high speed buffer implementation. The device includes a data register array containing empty data registers and imaginary FIFO queues, and an adminstrative register array comprised of a two port RAM for storing pointer chains specifying the imaginary FIFO queues. The input of data is accompanied by the modification of the pointer chain to extend it, whereas the output of data is accompanied by the modification of the pointer chain to shorten it, so that the imaginary FIFO queues are administered in flexible manner in order to achieve efficient memory capacity utilization. The procedure for controlling the imaginary FIFO queues can be executed in parallel because of the independency of read and write operations in the two port RAM.

REFERENCES:
patent: 4751675 (1988-06-01), Knauer
patent: 4833655 (1989-05-01), Wolf et al.
patent: 4839866 (1989-06-01), Ward et al.
Yuval Tamir et al., "High-Performance Multi-Queue Buffers for VLSI Communication Switches", Proceeding of International Conference on Computer Architecture '88, May 30-Jun. 2, 1988, pp. 343-354.

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