Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-12-20
1992-12-08
James, Andrew J.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307475, H03K 190175
Patent
active
051700727
ABSTRACT:
A buffer device having a booster circuit for a semiconductor memory device offers a solution to a deficient boost operation of the booster circuit due to a skew in an address signal. The buffer device has an address transition signal output circuit for outputting a HIGH signal for a specified time when detecting transition of an address signal, and a switching circuit for outputting to the booster circuit, in accordance with output from the address transition signal output circuit, either a data signal expressing data read from an address specified by the address signal or a precharge signal of a specified time length. The switching circuit, when receiving a HIGH signal from the address transition signal output circuit, outputs the precharge signal, and when receiving a LOW signal, outputs the data signal. The booster circuit boosts the data signal to a specified level when the data signal is HIGH. However, the booster circuit stops a boost operation and is precharged when the precharge signal is inputted. A transistor circuit is connected with the booster circuit for bringing, in response to output from the booster circuit, an electric potential of an output terminal of the buffer device and therefore of the semiconductor memory device to a specified high or low level in accordance with the output level from the booster circuit.
REFERENCES:
patent: 4583203 (1986-04-01), Monk
patent: 4612462 (1986-09-01), Asano et al.
patent: 4633102 (1986-12-01), Childers
patent: 4639622 (1987-01-01), Goodwin et al.
patent: 4724340 (1988-02-01), Sood
patent: 4769791 (1988-09-01), Liou et al.
patent: 4881201 (1989-11-01), Sato et al.
patent: 4905314 (1990-02-01), Kato et al.
patent: 4982113 (1991-01-01), Jinbo
patent: 4982117 (1991-01-01), Matsuzaki et al.
patent: 4985644 (1991-01-01), Okihara et al.
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5003205 (1991-03-01), Kohda et al.
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5017803 (1991-05-01), Yoshida
patent: 5056062 (1991-10-01), Kuwabara et al.
"Design For CMOS VLSI", Apr. 25, 1989, pp. 190-192.
"Semiconductor MOS Memories And Their Applications", Aug. 30, 1990, pp. 101-102.
"Dictionary Of LSI's", Jul. 30, 1988.
Sekino et al.: "Study of data output buffer"--The Spring Nation-wide Assembly of the Institute of Electronics, Information and Communication Engineers, 1988--pp. 1-3.
James Andrew J.
Sharp Kabushiki Kaisha
Tran Sinh
LandOfFree
Buffer device having a booster circuit for a semiconductor memor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buffer device having a booster circuit for a semiconductor memor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer device having a booster circuit for a semiconductor memor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-962515