Buffer descriptor structures for communication between...

Details Buffer descriptor structures for communication between... Buffer descriptor structures for communication between...

2011-06-28

2011-06-28

Wang, Andrew (Department: 2628)

Motion video signal processing for recording or reproducing

Video processing for recording

With compression

C345S502000

Reexamination Certificate

active

07970262

ABSTRACT:
A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

REFERENCES:
patent: 5479184 (1995-12-01), Tokumitsu
patent: 5717461 (1998-02-01), Hoogenboom
patent: 5771357 (1998-06-01), Kato et al.
patent: 5847718 (1998-12-01), Watson
patent: 6118491 (2000-09-01), Wu et al.
patent: 6438318 (2002-08-01), Adolph et al.
patent: 6614441 (2003-09-01), Jiang et al.
patent: 2001/0005398 (2001-06-01), Kono et al.
patent: 2001/0010708 (2001-08-01), Nakazawa
patent: 2002/0038443 (2002-03-01), Iwata et al.
patent: 2002/0196857 (2002-12-01), Kono et al.
patent: 2003/0137600 (2003-07-01), Chen et al.
patent: 2003/0206228 (2003-11-01), Trevers et al.
patent: 2004/0076236 (2004-04-01), Duruoz et al.
patent: 2004/0258160 (2004-12-01), Bhatia
patent: 2005/0083218 (2005-04-01), Regunathan et al.
patent: 2005/0093885 (2005-05-01), Savekar et al.

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