Buffer control system

Details Buffer control system Buffer control system

1996-05-22

1999-04-06

Vu, Huy D.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370412, H04J 302

Patent

active

058927620

ABSTRACT:
A buffer control system is a system for implementing both a priority control process and a shaping process of cells with a hardware configuration of a small size in a network routing fixed-length packets which are respectively composed of transfer data and control information added to the transfer data, and to which priority information is assigned, according to the control information. If a cell written to an empty area of a cell buffer is a prioritized cell, and its expected output time is a time slot, an address where the cell is stored in the cell buffer is arranged in a time slot in a prioritized cell entry memory. When it reaches the time to read the cell stored in the time slot, the address stored in the time slot is written to an output list chain, and the cell is read from that address. The empty area of the buffer is managed using a free list chain.

REFERENCES:
patent: 5233606 (1993-08-01), Pashan et al.
patent: 5253251 (1993-10-01), Aramaki
patent: 5499238 (1996-03-01), Shon
patent: 5555264 (1996-09-01), Sallberg et al.
patent: 5640389 (1997-06-01), Masaki et al.
Eugen Wallmeier and Tom Worster; The Spacing Policer, An Algorithm for Efficient Peak Bit Rate Control in ATM Networks; Oct. 1992.

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