Buffer circuits for use with semiconductor memory devices

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307269, 307481, 307353, 307272A, 307575, 307279, H03K 17687, G11C 1140

Patent

active

045423067

ABSTRACT:
In a buffer circuit for producing two output signals of the opposite phases in response to an input signal comprising a pre-circuit producing two pre-output signals in accordance with the input signal and a reference voltage signal; and a main circuit including a latch circuit latching the pre-output signals, and a flip-flop circuit connected to receive the pre-output signals latched by the latch circuit for producing the output signals of the buffer circuit, there is provided a transfer gate circuit enabled by the pre-output signals and disabled by the output signals of the buffer circuit. According to this invention, different from the prior art circuit, it is not necessary to use any clock signal having a high level at the time of operation of the buffer circuit and to have strict time spacing, whereby the clock signal generator can be simplified and the buffer circuit can be miniaturized and its operating speed can be increased.

REFERENCES:
patent: 4238841 (1980-12-01), Clemen et al.
patent: 4354257 (1982-10-01), Varshney et al.
patent: 4396845 (1983-08-01), Nakano
patent: 4397000 (1983-08-01), Nagami
patent: 4417163 (1983-11-01), Otsuki et al.
patent: 4441039 (1984-04-01), Schuster

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