Buffer circuits

Details Buffer circuits Buffer circuits

1981-02-17

1983-11-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307356, 307482, 307578, 365203, 365230, H03K 19092, H03K 17693, G11C 800

Patent

active

044171633

ABSTRACT:
The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.

REFERENCES:
patent: 4077031 (1978-02-01), Kitagawa et al.
patent: 4110639 (1978-08-01), Redwine
patent: 4291246 (1981-09-01), Martino, Jr. et al.
Paul R. Schroeder and Robert J. Proebsting "A 16K.times.1 Bit Dynamic RAM", pub. --Digest of Technical Papers of the 1977 IEEE International Solid--State Circuits Conference, pp. 12 and 13.

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