Buffer circuitry

Details Buffer circuitry Buffer circuitry

1999-04-05

2001-11-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C327S039000, C327S042000, C226S016000, C226S087000

Reexamination Certificate

active

06313669

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to buffer circuitry for temporarily storing a data and for furnishing the data to its output terminal.
2. Description of the Prior Art
Referring now to FIGS.
34
(
a
) and
34
(
b
), there are respectively illustrated diagrams showing a method of testing prior art buffer circuitry when a data applied to the buffer circuitry makes a HIGH to LOW transition and when the data makes a LOW to HIGH transition. In the figures, reference numeral
1
denotes the waveform of a data furnished by way of an output terminal of prior art buffer circuitry, which makes a HIGH to LOW transition,
2
denotes the waveform of the clock signal (CLK), VOL denotes a first threshold voltage that is used when a data furnished via the output terminal makes a HIGH to LOW transition,
4
denotes the waveform of a data furnished by way of the output terminal of the buffer circuitry, which makes a LOW to HIGH transition, and VOH denotes a second threshold voltage that is used when a data furnished via the output terminal makes a LOW to HIGH transition.
When the buffer circuitry receives an incoming signal at a HIGH level, it can furnish an output signal at a HIGH level by way of its output terminal. In contrast, when the buffer circuitry receives an incoming signal at a LOW level, it can furnish an output signal at a LOW level by way of its output terminal. The buffer circuitry can be tested to check the operation of the buffer circuitry in the following manner.
First, a test to check the operation of the buffer circuitry on falling edges of incoming data is carried out by applying a data at a LOW level to the buffer circuitry in synchronization with a rising edge of CLK (in the example of FIG.
34
(
a
), the data is input to the buffer circuitry at point a). The potential of the data furnished by way of the output terminal of the buffer circuitry start decreasing gradually since point a.
A volt-ohm-millimeter or the like connected to the output terminal of the buffer circuitry can measure the potential of the data furnished by way of the output terminal of the buffer circuitry at a strobe point b and then compare the potential of the data measured at the strobe point with the first threshold voltage VOL after the buffer circuitry has received the data at a LOW level.
Thus it can be determined that the buffer circuitry operates well when the test instrument indicates that the measured potential of the output data is lower than or equal to the first threshold voltage VOL; otherwise, that is, when the test instrument indicates that the measured potential of the output data is higher than the first threshold voltage VOL, the buffer circuitry is at fault.
Further, a test to check the operation of the buffer circuitry on rising edges of incoming data is carried out by applying a data at a HIGH level to the buffer circuitry in synchronization with a rising edge of CLK (in the example of FIG.
34
(
b
), the data is input to the buffer circuitry at point c). The potential of the data furnished by way of the output terminal of the buffer circuitry start increasing gradually since point c.
The test instrument connected to the output terminal of the buffer circuitry can measure the potential of the data furnished by way of the output terminal of the buffer circuitry at a strobe point d, and then compare the potential of the data measured at the strobe point with the second threshold voltage VOH after the buffer circuitry has received the data at a HIGH level.
Thus it can be determined that the buffer circuitry operates well when the test instrument indicates that the measured potential of the output data is higher than or equal to the second threshold voltage VOH; otherwise, that is, when the test instrument indicates that the potential of the output data is lower than the second threshold voltage VOH, the buffer circuitry is at fault.
Although a prior art technique for improving the driving capability of buffer circuitry when testing the buffer circuitry is disclosed in Japanese Patent Application Publication (KOKAI) No. 2-26412, it is not adapted to improve the driving capability of the buffer circuitry according to a change in the frequency of the clock signal CLK.
A problem with prior art buffer circuitry, which is so constructed as mentioned above, is that although the settings of the strobe point and the first and second threshold voltages according to the frequency of CLK make it possible to properly check the operation of the buffer circuitry, a test program to set the strobe point and the first and second threshold voltages has to be changed every time the frequency of CLK is varied, thereby preventing a speedup in the checking of the operation of the buffer circuitry.
SUMMARY OF THE INVENTION
The present invention is made to overcome the above problem. It is therefore an object of the present invention to provide buffer circuitry for making it possible to check the operation of the buffer circuitry speedily even if the frequency of a clock signal CLK is varied.
In accordance with one aspect of the present invention, there is provided buffer circuitry for receiving a data applied thereto and furnishing a signal corresponding to the received data by way of an output terminal, the buffer circuitry comprising: a data output circuit for connecting a first power supply to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level; a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency; and a driving capability changing circuit for, only if the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the reference frequency, connecting a second power supply to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level. The buffer circuitry can have a mechanism for activating the driving capability changing circuit only if the buffer circuitry is placed in test mode to check for operation of the buffer circuitry.
In accordance with another aspect of the present invention, there is provided buffer circuitry comprising: a data output circuit for receiving a data applied thereto and for furnishing the data received to an output terminal; a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency; and a driving capability changing circuit for connecting a power supply to the output terminal when the data is at a HIGH level, and for connecting a ground to the output terminal when the data is at a LOW level, only if the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the reference frequency. The buffer circuitry can have a mechanism for activating the driving capability changing circuit only if the buffer circuitry is placed in test mode to check for operation of the buffer circuitry.
In accordance with another aspect of the present invention, there is provided buffer circuitry for receiving a data applied thereto and furnishing a signal corresponding to the received data by way of an output terminal, the buffer circuitry comprising: a data output circuit for connecting a power supply line to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level; a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency; and a driving capability changing circuit for connecting a first power supply to the power supply line when the comparator outputs a comparison result indicating that the frequency of the clock signal is less than or equal to the reference frequency, or connecting a second power supply having a higher potential than the first power supply to the power supply line when the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the refere

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