Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-04-10
2001-05-15
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S309000, C327S328000
Reexamination Certificate
active
06232805
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to buffer circuits for analog signals, and in particular, buffer circuits having voltage clamping features.
BACKGROUND OF THE INVENTION
Buffering and clamping analog signals are important operations in many analog and mixed-signal circuits. One common buffer circuit utilizes a pair of MOS transistors, with one transistor being in the source-follower configuration and the second transistor operating as a current source coupled to the source electrode of the first transistor. This source follower circuit provides a gain of approximately one.
FIG. 1A
is another exemplary prior art buffer circuit
6
which provides a more precise gain of one.
FIG. 1B
shows the output of the buffer circuit
6
connected to the input a circuit
8
which performs further processing of the buffered output. Circuit
8
can perform almost any type of operation on the buffered output, including, by way of example, a line driver circuit, a comparator circuit or the like.
The
FIG. 1A
circuit
6
includes a pair of NMOS input transistors M
1
and M
2
which are connected as a differential pair. A tail current source, comprising NMOS transistor M
4
, is coupled to the common source connections of transistors M
1
and M
2
. A PMOS load transistor M
3
, which operates in the saturation region, is connected between input transistor M
2
and the supply VDD. The output Out of the buffer circuit is at the node intermediate input transistor M
2
and load transistor M
3
. The differential amplifier has a relatively high open loop gain. A direct feedback connection is made from the output back to the inverting input of the differential amplifier, the gate of transistor M
2
, which sets the gain to be close to one.
In some applications, it is desirable to be able to clamp the output of the buffer circuit so that the output does not exceed some maximum and some minimum predetermined values. The prior art circuit
6
of
FIG. 1A
does not provide these capabilities. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention successfully addresses this shortcoming of the prior art.
SUMMARY OF THE INVENTION
A buffer circuit arrangement having voltage clamping capabilities is disclosed. The buffer circuit output generally follows the input until the input approaches either first or second clamping voltages, at which point the output no longer follows the input but remains clamped at either a lower or an upper level deter mined by first and second clamping voltages.
The buffer circuit is connected between first and second power supply rails and includes an input MOS transistor having a gate for receiving the input voltage to be buffered. A current source is connected intermediate a source of the input transistor and the first power supply rail. A first clamping transistor is provided having a source coupled to the source of the input transistor and a gate for receiving the first clamping voltage. A second clamping transistor is also provided connected in series with the input transistor and having a gate for receiving the second clamping voltage.
In one embodiment, the buffer circuit is configured as a source follower circuit having an output which is located at the source of the input transistor. The output is coupled to a subsequent circuit which performs further processing on the buffered output. In another embodiment, the buffer circuit is implemented as a differential amplifier, with one side including the input transistor and the first and second clamping transistors. The output is located on the other side of the differential amplifier.
REFERENCES:
patent: 5550446 (1996-08-01), Schlager et al.
patent: 5905617 (1999-05-01), Kawasoe
patent: 5973561 (1999-10-01), Heaton
patent: 6005438 (1999-12-01), Shing
patent: 6150881 (2000-11-01), Lovelace et al.
Girard & Equitz LLP
National Semiconductor Corporation
Tran Toan
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