Buffer circuit with reduced power consumption

Details Buffer circuit with reduced power consumption Buffer circuit with reduced power consumption

2006-06-08

2009-12-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S083000

Reexamination Certificate

active

07626428

ABSTRACT:
A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation.

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Moon, et al., “2-inch qVGA SOG-LCD employing TS-SLS”, Digest of Technical Papers, AM-LCD04, 2004, Active Matrix Liquid Crystal Display Device Workshop, Aug. 25-27, 2004.

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