Buffer circuit with programmable switching thresholds

Details Buffer circuit with programmable switching thresholds Buffer circuit with programmable switching thresholds

2003-03-03

2004-09-28

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S112000

Reexamination Certificate

active

06798267

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to buffer circuits for interfacing between different logic families.
Many electronic systems use buffer circuits to interface between devices from different logic families. For example, a buffer circuit may be used to interface between a transistor-transistor logic (TTL) microprocessor unit (MPU) and a complementary metal-oxide-semiconductor (CMOS) memory device. The CMOS and TTL logic families have distinct switching thresholds in order to operate with the maximum noise immunity.
TTL logic circuits are specified to have a “zero logic level” from zero to 0.8 volt, and a “one logic level” from two volts to five volts. In order to provide a high noise immunity, a buffer circuit is specified to have a switching threshold of 1.4 volts, which is the middle of the TTL switching range.
CMOS logic circuits operate with a supply voltage up to about sixteen volts, and the logic levels are percentages of the supply voltage, with voltage levels from ground to 30% of the supply voltage being a “zero logic level”, and voltage levels from 70% of the supply voltage to the supply voltage being a “one logic level”. Hence, if the supply voltage is 3.3 volts, which is a common level in modern low power systems, a “zero logic level” has a range of zero to 0.55 volts, and a “one logic level” has a range of 2.75 volts to 3.3 volts. Typically, a circuit receiving CMOS logic levels has a voltage threshold of fifty percent of the supply voltage or 1.65 volts for a 3.3 volt supply voltage.
Most previous buffer circuits have a single switching threshold that is set to a level of one logic family. Thus, two different buffer circuits, each specified to receive signals from one logic family, are required in order for the MPU and memory circuits to transfer data to each other. The two buffer circuits require the manufacturing of two distinct semiconductor die, which requires the tracking of two part numbers and reduces the economies of scale and therefore increases the cost of each buffer circuit.
Hence, there is a need in the industry for a single buffer circuit that can be programmed for two distinct switching thresholds.


REFERENCES:
patent: 6175251 (2001-01-01), Horiguchi et al.
patent: 6255867 (2001-07-01), Chen
patent: 6573781 (2003-06-01), Brueckner
patent: 0405833 (1991-01-01), None

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