Buffer circuit using low voltage transistors and level shifters

Details Buffer circuit using low voltage transistors and level shifters Buffer circuit using low voltage transistors and level shifters

2002-08-27

2004-10-05

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S333000, C326S063000, C326S083000

Reexamination Certificate

active

06801064

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic circuits and more particularly to a buffer circuit.
BACKGROUND OF THE INVENTION
Semiconductor processing techniques are constantly improving and as they improve the required power supply voltages are reduced. The best semiconductor processing techniques today only require power supply voltages of around 1.8 volts. These processing techniques create transistors commonly referred to as thin oxide transistors. Thin oxide transistors are faster and can be used to produces denser circuits. Unfortunately, thin oxide circuits commonly have to interface with older technology circuits that have high voltage power supplies (e.g., 2.5V, 3.0V or 3.3V). These high voltage circuits contain transistors commonly referred to as thick oxide transistors. When it is necessary that a signal be transmitted from a low voltage thin oxide circuit to a high voltage, thick oxide circuit, a buffer circuit is required to convert the signal from a low voltage to a higher voltage; Prior art solutions use a buffer circuit that has both thick oxide transistors (components) and thin oxide transistors (components). As a result, the processing of these circuits is complex and expensive. Another problem with prior art circuits is that they have crowbar current. A crowbar current occurs when the output of the buffer circuit transitions and current flows directly from the power supply to ground.
Thus there exists a need for a buffer circuit that overcomes the problems of the prior art circuits.
SUMMARY OF INVENTION
A buffer circuit that overcomes these and other problems has a level translator circuit includes transistors having only thin oxides. A driver is coupled to the level translator circuit. The driver has transistors that are all thin oxide type transistors. The driver has a high voltage output. In one embodiment, the level translator circuit has a bias input and a data input. In another embodiment, the bias input includes a p-channel bias input and an n-channel bias input.
In one embodiment, the driver circuit includes a plurality of p-channel transistors coupled between a high voltage power supply and the high voltage output. In another embodiment, the driver circuit includes a plurality of n-channel transistors coup led between the high voltage output and a ground voltage.
The level translator circuit has a pull-up output signal and a pull-down output signal, in one embodiment. The pull-up output signal transitions off before the pull-down output signal transitions on when a data signal transitions from a high logic level to a low logic level, in one embodiment.
In one embodiment, the buffer circuit has a pull-up level shifter coupled to an input signal. A pull-down level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter. In one embodiment, the driver has a tri-state. In another embodiment, the driver does not have a crowbar current when an output of the driver transitions. In one embodiment, the pull-up level shifter is formed with transistors that are all thin oxide type transistors. In another embodiment, the output of the driver circuit has a high voltage output. In one embodiment, the driver has transistors that are all thin oxide type transistors. In another embodiment, the pull-up level shifter is coupled to a bias input signal. The pull-up level shifter is coupled to an enable input signal, in one embodiment.
In one embodiment, the buffer circuit has a first leg that contains a plurality of thin oxide transistors, coupled to a high voltage power supply. The first leg is coupled to an input signal. A second leg is symmetrical to the first leg and is coupled to the first leg at the high voltage power supply. The second leg has an output. In one embodiment, the first leg is coupled to a bias signal. In another embodiment, the second leg has a group of p-channel transistors coupled to the high voltage power supply and a group of n-channel transistors coupled between the p-channel transistors and a ground. The output of the second leg is coupled between the group of p-channel transistors and the group of n-channel transistors in one embodiment. One of the thin oxide transistors of the first leg is cross coupled with a transistor of the second leg in one embodiment.


REFERENCES:
patent: 5300832 (1994-04-01), Rogers
patent: 5539334 (1996-07-01), Clapp et al.
patent: 5821800 (1998-10-01), Le et al.
patent: 5892371 (1999-04-01), Maley
patent: 6240027 (2001-05-01), Lee et al.
patent: 6292025 (2001-09-01), Okumura
patent: 6501306 (2002-12-01), Kim et al.

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